// div50to2p048
// 50M分频2.048M

module div50to2p048 (input clk_50,
                     rst_n,
                     output reg clk_2p048);
    
    reg [4:0] cnt1;
    
    always @(posedge clk_50 or negedge rst_n) begin
        if (!rst_n) begin
            cnt1      <= 0;
            clk_2p048 <= 0;
        end
        else if (cnt1 < 11) begin
            cnt1 <= cnt1 + 1;
        end
        else begin
            cnt1      <= 0;
            clk_2p048 <= ~clk_2p048;
        end
    end
    
endmodule
